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[PARENTDIR]Parent Directory   -
[DIR]acs/ 2024-12-18 18:34 -
[DIR]atlc/ 2024-12-18 18:34 -
[DIR]boolean/ 2024-12-18 18:34 -
[DIR]cascade/ 2024-12-18 18:34 -
[DIR]covered-current/ 2024-12-18 18:34 -
[DIR]covered/ 2024-12-18 18:34 -
[DIR]dinotrace-mode/ 2024-12-18 18:34 -
[DIR]dinotrace/ 2024-12-18 18:34 -
[DIR]eagle/ 2024-12-18 18:34 -
[DIR]electric/ 2024-12-18 18:34 -
[DIR]fastcap/ 2024-12-18 18:34 -
[DIR]fasthenry/ 2024-12-18 18:34 -
[DIR]felt/ 2024-12-18 18:34 -
[DIR]geda-docs/ 2024-12-18 18:34 -
[DIR]geda-symbols/ 2024-12-18 18:34 -
[DIR]geda-utils/ 2024-12-18 18:34 -
[DIR]geda/ 2024-12-18 18:34 -
[DIR]gerbv/ 2024-12-18 18:34 -
[DIR]gnetlist/ 2024-12-18 18:34 -
[DIR]gnucap/ 2024-12-18 18:34 -
[DIR]gschem/ 2024-12-18 18:34 -
[DIR]gsymcheck/ 2024-12-18 18:34 -
[DIR]gtkwave/ 2024-12-18 18:34 -
[DIR]gwave/ 2024-12-18 18:34 -
[DIR]ipal-current/ 2024-12-18 18:34 -
[DIR]libgeda/ 2024-12-18 18:34 -
[DIR]magic/ 2024-12-18 18:34 -
[DIR]ng-spice/ 2024-12-18 18:34 -
[DIR]oregano/ 2024-12-18 18:34 -
[DIR]pcb-current/ 2024-12-18 18:34 -
[DIR]py-MyHDL/ 2024-12-18 18:34 -
[DIR]qcad/ 2024-12-18 18:34 -
[DIR]simian/ 2024-12-18 18:34 -
[DIR]spice/ 2024-12-18 18:34 -
[DIR]tkgate/ 2024-12-18 18:34 -
[DIR]transcalc/ 2024-12-18 18:34 -
[DIR]verilog-current/ 2024-12-18 18:34 -
[DIR]verilog-mode/ 2024-12-18 18:34 -
[DIR]verilog/ 2024-12-18 18:34 -
[DIR]vipec/ 2024-12-18 18:34 -
[DIR]xchiplogo/ 2024-12-18 18:34 -
[DIR]xcircuit/ 2024-12-18 18:34 -